Silicon carbide (SiC) power devices, and, in particular, silicon carbide high power devices, provide advantages such as high switching speed and low power losses. Examples of highly-efficient SiC power devices include (but are not limited to) rectifiers, field-effect transistors (FETs) and bipolar Junction Transistors (BJTs). Multiple physical properties are responsible for the various advantages of silicon carbide high power devices, such as their high critical field for avalanche breakdown.
As a result, for example, a high voltage of between 800V and 4500V can be blocked within a very thin layer of, e.g., between approximately 4 μm and 35 μm. Mechanical stability considerations dictate a typical SiC substrate thickness of at least between approximately 300 to 500 um during at least some processing contexts, although such thicknesses may be higher than that required from the standpoint of electrical device function. That is, for example, electrical and thermal resistance of excessively thick substrates tends to impact the performance of SiC high power devices.
To mitigate such impacts, it is possible to perform thinning of at least a portion of the SiC substrate. Such thinned-down SiC substrates, as just referenced, may not be preferable or feasible during topside semiconductor processes, e.g., used to form active device structures. In particular, a 150-mm or larger SiC substrate that is thinner than approximately 280 μm may be incompatible with front-end SiC device processing in a wafer fabrication setting. Instead, wafer thinning may be performed at the stage at which the topside active structure is complete (or almost complete). As a result, wafer process post thinning may be limited to particular operations, such as Ohmic contact formation, followed by deposition of a solder metal. Annealing of the backside contact to achieve the desired Ohmic behavior and low contact resistance may be done in such scenarios using a source of pulsed energy, such as a pulsed laser with a pulse duration of a few nanoseconds to a few hundred nanoseconds. The contact anneal may then be followed by deposition of a solder metal stack.
A specific feature of SiC is that Ohmic contact formation typically requires a temperature of between approximately 850 C and 1050 C. This is particularly true for forming a nickel silicide (NiSix) contact, which provides low resistivity and good process stability. Nickel silicide can be formed on silicon carbide through reaction of SiC with metallic nickel, in a manner that is similar to that for formation of nickel silicide on silicon. On silicon carbide, this reaction is accompanied by release of excessive carbon, part of which carbon is captured at the SiC to NiSix interface, and part of which diffuses into the silicide to form carbon clusters in the bulk of the silicide, as well as on the free surface of the silicide. The carbon trapped at the SiC/NiSix interface is reported to have a structure of multiple-layer graphene, and advantageously forms an interface with a low barrier to SiC. Thus, this low barrier of carbon to the SiC is considered to be responsible for, or related to, the desired Ohmic properties of the NiSix contact on SiC.
However, excessive carbon production, and distribution thereof within the silicide, may result in a number of problems and difficulties. For example, such problems and difficulties may include poor metal adhesion (and lack of stability of resulting contact) for the contacts formed by furnace or by rapid thermal processing (RTP) anneal.